1. Field of the Invention
The present invention relates to a liquid crystal display device and more particularly to a shift register with low capacitance loading with overlapping outputs and a liquid crystal display device using the same.
1. Discussion of the Related Art
A liquid crystal display device controls the light transmittance of liquid crystal cells in accordance with a video signal to display a picture.
In an active matrix type liquid crystal display device, active switching devices are used to control the electric fields in each liquid crystal cell to control the light transmittance of the cell. By controlling the active switching devices, moving images can be displayed. Thin film transistors (hereinafter, referred to as ‘TFTs’) are primarily used as the switching devices in an active matrix type liquid crystal display device.
A liquid crystal display device of the related art, as shown in FIG. 1, includes a liquid crystal display panel 2 having a plurality of data lines 5 crossing a plurality of gate lines 6 with TFTs for driving liquid crystal cells formed at the crossings of the gate and data lines; a data driver 3 for supplying data to the data lines 5; a gate driver 4 for supplying a scan pulse to the gate lines 6; and a timing controller 1 for controlling the data driver 3 and the gate driver 4.
The liquid crystal display panel 2 includes liquid crystal injected between two glass substrates. The data lines 5, gate lines 6 and TFTs are formed on a lower of the two glass substrates. The TFTs supply the data from the data lines 5 to the liquid crystal cell in response to the scan pulse from the gate lines 6. To this end, a gate electrode of the TFT is connected to the gate line 6, a source electrode is connected to the data line 5, and, a drain electrode of the TFT is connected to a pixel electrode of the liquid crystal cell Clc. Further, a storage capacitor Cst for maintaining the voltage of the liquid crystal cell is formed on the lower glass substrate of the liquid crystal display panel
The data driver 3 includes a plurality of data integrated circuits hereinafter, referred to as ‘ICs’), and each of the data ICs includes a shift register; a register for temporarily storing stretched digital video data RGB from the timing controller 1; a latch for storing the data line by line and outputting the stored data of one line at the same time in response to a clock signal from the shift register; a digital/analog converter for selecting a positive/negative analog gamma compensation voltage in correspondence to a digital data value from the latch; a multiplexer for selecting the data line 5 to which the positive/negative gamma compensation voltage is supplied; and an output buffer connected between the multiplexer and the data line. The data driver 3 supplies the digital video data RGB from the timing controller 1 to the data lines 5 of the liquid crystal display panel 7.
The gate driver 4 includes a shift register for sequentially generating a scan pulse in response to a gate control signal GDC from the timing controller 1; a level shifter for shifting a swing width of the scan pulse to a level suitable for driving the liquid crystal cell Clc; and an output buffer. The gate driver 4 supplies the scan pulse to the gate line 6 to turn on the TFTs connected to the gate line 6, thereby selecting the liquid crystal cells Clc of a horizontal line to which a pixel voltage of the data, i.e., analog gamma compensation voltage, is to be supplied. The data generated from the data driver 3 are supplied to the liquid crystal cell Clc of the horizontal line selected by the scan pulse.
The timing controller 1 receives a digital video data RGB, a horizontal synchronization signal H, a vertical synchronization signal H, and a clock signal CLK to generate a gate control signal GDC for controlling the gate driver 4 and a data control signal DDC for controlling the data driver 3. Further, the timing controller 1 supplies the data RGB to the data driver 3.
On the other hand, in order to reduce the number of integrated circuits of the data driver, as shown in FIG. 2, there has been proposed a liquid crystal display device having common bus lines 201 to 240 connected to an output terminal of the data register 21 in a one-to-one relationship, and a channel selecting part 24 and a sampling & holding part 23 disposed between the common bus lines 201 to 240 and the data lines DL1 to DL42. A plurality of data output bus lines are formed in each of the common bus lines 201 to 240. For example, the first and 41st data output bus lines 301, 341 are connected to the first common bus line 201. The channel selecting part 24 includes a plurality of switch devices 24A that are connected to the data output bus lines 301 in the one-to-one relationship. The switch devices 24A for the channel selecting part 24 may be realized using CMOS structures and are sequentially turned on in response to the control signal from the shift register 22, thereby acting to supply the data from the data output bus lines 301 to the sampling & holding part 23. The sampling & holding part 23 sequentially samples and holds the data from the channel selecting part 24, and then simultaneously supplies the held data to the data lines DL1 to DL42.
A shift register for making the switch devices 24A of the channel selecting part 24 sequentially operated may be realized as shown in FIG. 3 or FIG. 5.
FIG. 3 illustrates a stage configuration for a shift register 22 allowing overlapped output pulses. FIG. 4 illustrates input/output waveforms of the shift register 22 shown in FIG. 3.
Referring to FIG. 3 and 4, an arbitrary stage of the shift register 22 includes a first inverter type tri-state buffer 31, a first latch 37, a second inverter type tri-state buffer 34 and a second latch 38 disposed in cascade between an input terminal and an output terminal. Each stage of the shift register 22 outputs a start pulse or an output pulse (in) of a previous stage by delaying it for as much as one clock period in response to first and second clock signals (cka, ckb) which have opposite phases, and generates the output pulse (in) which overlaps the output pulse (in) of the previous stage by as much as one clock period.
The first clock signal (ckb) is inputted to a non-inversion control terminal of the first inverter type tri-state buffer 31 and the second clock signal (cka) is inputted to an inversion control terminal of the first inverter type tri-state buffer 31. The start pulse or the output pulse (in) of the previous stage is inputted to the input terminal. The first inverter type tri-state buffer 31 inverts the output pulse (in) of the previous stage or the start pulse to supply to the first latch 37 when the first clock signal (cka) of logic high is supplied to the non-inversion control terminal and the second clock signal (ckb) of logic low is supplied to the inversion control terminal. The first inverter type tri-state buffer 31 is changed to a high impedance state so as not to transmit the start pulse of the output pulse (in) of the previous stage to the first latch 37 when the first clock signal (cka) a logic low level is supplied to the non-inversion control terminal or the second clock signal (ckb) of logic high level is supplied to the inversion control terminal.
The first latch 37 includes a first inverter 32 and a third inverter type tri-state buffer 33 which are connected within a closed loop between the first inverter type tri-state buffer 31 and the second inverter type tri-state buffer 34. The first latch 37 latches the output of logic high, inverts the output and supplies the inverted output to the second inverter type tri-state buffer 34 when the output of the first inverter type tri-state buffer 31 is at logic high.
The second inverter type tri-state buffer 34 inverts the output from the first latch 37 to supply to the second latch when the second clock signal (ckb) of a logic high level is supplied to the non-inversion control terminal and the first clock signal (cka) of logic low level is supplied to the inversion control terminal at the same time.
The second latch 38 includes a second inverter 35 and a fourth inverter type tri-state buffer 36 which are connected within a closed loop between the second inverter type tri-state buffer 34 and an output terminal. The second latch 38 latches the output of logic high, inverts the output, and supplies the inverted output to the output terminal and simultaneously generates a start pulse (In+1) for the next shift register stage when the output of the second inverter type tri-state buffer 34 is at a logic high level.
As shown in FIG. 4, the outputs S1 to S42 of the stages are shifted while being overlapped by as much as one clock period. The outputs S1 to S42 sequentially turn on the switch devices 24A that are included in the channel selecting part 24 shown in FIG. 2.
The shift register configured with the stages as illustrated in FIG. 3 has an advantage that the operating speed of the channel selecting part 24 can be increased by the amount of the overlapping period between the shifted outputs. On the other hand, such a shift register has a problem that a capacitance between the gate terminal and the source/drain is relatively high because a clock signal line is connected to the gate terminal of an MOS TFT used for each of the inverter type tri-state buffers. The high capacitance generates signal delays that limit the usable frequency of the clock signal. Further, the high capacitance causes increased power consumption if the drive voltage is increased to operate at high speeds.
FIG. 5 illustrates one stage a shift register 22 having a configuration in which the output pulses are not overlapped.
Referring to FIG. 5, an arbitrary stage of the shift register 22 includes a first multiplexer 51, an OR circuit 52, a second multiplexer 53, and first to fifth inverters 54 to 58.
Each of the multiplexers 51 and 53 has a circuit configuration in which two transmission gates are symmetrically connected, and the multiplexer outputs an input signal applied to a first input terminal (in1) when a logic high signal is supplied to a non-inversion control terminal but outputs an input signal applied to a second input terminal (in2) when a logic high signal is supplied to an inversion control terminal.
The OR circuit 52 includes an NOR gate having two input terminals and an inverter. The output of the first inverter 54 is supplied to the second input terminal of the NOR gate as feedback and the output of the first multiplexer 51 is supplied to the first input terminal of the NOR gate. The OR circuit inverter inverts the output of the NOR gate. The OR circuit 52 generates an output which is a logical sum (OR) of the two input terminals to the NOR gate.
The shift register 22, using the shift register stages illustrated in FIG. 5, has an advantage that the capacitance load is low because the clock signal line is connected to the source/drain terminal of the MOS TFT which constitutes the transmission gate and because most of the MOS TFTs are in an off state during operation. However, a shift register 22 employing register stages as illustrated in FIG. 5 has the problem that outputs cannot be overlapped.